Variable interval timer circuit

ABSTRACT

A circuit employing relatively small capacitances to provide an output signal for a predetermined, variable time period measured from the closing of a control switch.

Umted States Patent 1 1 1 1 3,814,954

Cake 1 June 4, 1974 54] VARIABLE INTERVAL TIMER CIRCUIT 3,105,!58 9/1963Nichols 307/227 X 3, 1 -1 memo Arthur Cake, smnhwwm Long 3.15%.??? 35321$1321? 39.367732; Island, N.Y- 3,171,041 2/1965 Haase 307/293 X3,204,153 8/1965 Tygart 307/293 X [73] Ass'gnee' gig?" g Cmpmamn3,351,781 l1/l967 Johnson .1 307/225 R Wan) 3,378,697 4/1968 Prestonetal .1307/227 x [22] l M 19, 1972 3.378,698 4/1968 Kadah 307/227 X [21]App]. No.: 255,137 I Prtmury Exammer-Stanley D. Mlller, Jr. Attorney,Agent, or Firm'Eyre, Mann & Lucas [521 US. Cl 307/293, 307/227, 307/246,

328/129, 328/186 [51] int. Cl. H03k 17/26 [57] ABSTRACT [58] Field ofSearch 307/225 R, 227, 293, 246;

v 328/39 186 129 A c1 rcu1t employmg relatwely small capacltanctts t0provlde an output stgna] for a predetermmed, vanable [56] ReferencesCited time period measured from the closing of a control UNITED STATESPATENTS 2.873.388 2/]959 Trumbo 307/227 X 9 Claims, 1 Drawing Figure HalD6 f/flVDC fit M HOVDC I" "1 /I I (am/mum 1 P/ [j 20/10 I (flea/a- 1 4('4 I I 1 l I l I 1 I I I 1 142 i l l I l l 1 VARIABLE INTERVAL TIMERCIRCUIT CROSS-REFERENC E TO RELATED APPLICATION The present inventionadvantageously incorporates a pulse generator of the type disclosed andclaimed in copending US. Pat. application Ser. No. 255,155 forELECTRONIC TIMING CIRCUITS filed on May 19, 1972 in the name of Paul A.Carlson.

BACKGROUND OF THE INVENTION Numerous prior art circuits have beendevised to carry out the function of providing an output signal, whichmay be utilized for control purposes, for a predetermined, variable timeperiod from the application of an input signal. The input signal maycomprise a change in a voltage or current level, or the opening orclosing of a switch. Typically, when long time periods on the order ofseveral minutes are desired, such prior art circuits would employ verylarge capacitors in an RC charging or discharging circuit. Suchcapacitors-are expensive, bulky and usually exhibit a high degree ofsensitivity to variations in ambient temperatures. In addition, manyprior art circuits employ semiconductor devices which are variablyconductive during the timing operation, thereby making the circuitunstable due to variations in leakage currents and othertemperature-dependent characteristics.

SUMMARY OF THE INVENTION The present invention is embodied in andcarried out by a circuit which is operative to provide an output signalfor a predetermined, variable time period measured from the initiationof application of an input signal. The circuit embodying the presentinvention employs relatively small, non-electrolytic capacitors, therebykeeping component size and cost low and reliability high. In addition,the semiconductor devices employed in the timing portion of applicantscircuit are normally in a saturated or cut-off condition during thetiming operation, so that circuit functioning is not adversely affectedby fluctuations in ambient temperature.

BRIEF DESCRIPTION OF THE DRAWING DESCRIPTION OF THE PREFERRED EMBODIMENTReferring now to the drawing, the circuit incorporates a pulse generatorwhich is operative to provide substantially rectangular output pulses ofbrief duration and having a relatively low frequency, e.g.,approximately l hertzuln the pulse generator which is preferred in thepresent application, such pulses may be derived, as shown, from both theemitter of transistor 01 and the collector of transistor 02. The pulsetrains derived at these two points in the pulse generator 10 are in'synchronization with one another. This pulse generator is part of thesubject matter of the crossreferenced application.

When the circuit shown in the drawing is energized by a +10 volt sourceas indicated, the pulse generator 10 will continually generate theaforementioned synchronous pulse trains. The transistor switch formed bythe complementary transistor pair 03-04 connected in the regenerativefeedback configuration is maintained conductive by'sustaining currentpassing through resistance R8, diode D2 and the switch 03-04. Transistor05 is normally non-conductive, since the bias voltage provided byvoltage divider R5 and R6 is too low because R6 is connected in parallelwith the conductive transistor switch 03-04. This same shunt pathdiverts the pulses fed to timing capacitance C4 through diode D1,leaving C4 uncharged.

Consequently, charging of C4 is initiated. The pulses derived at thecollector of transistor 02 are differentiated by C2 and R4, at thejunction of which appear pulses in the form of spikes, havingalternately positive and negative polarities. Only the positive pulsesthus developed will pass through diode D1 to charge C4. Thus, thecombination of C2, R4 and DI operates as a frequency divider by halvingthe number of pulses which are produced by pulse generator I0, andreduces 'the amount of charge placed on C4 by each of those pulses.

Thevoltage on C4 will subsequently rise at a relatively slow rate.Because the transistor switch 03-04 responds more predictably to suddenchanges in voltage rather than a slow-rising voltage, it has been foundto be advantageous to feed the synchronous pulse train derived at theemitter of transistor 01 through seriesconnected resistance R9 andcapacitance C3 to the base of transistor 03. Thus, after each incrementof charge has been added to capacitance C4 by the pulses passing throughdiode D1, thereby raising the voltage at the emitter of transistor 03,this increase is immediately followed by a sharp decrease in the voltageat the base of 03, thereby facilitating turn-on of the transistor switch03-04 when C4 has become sufficiently charged.

Once the transistor switch 03-04 has again been rendered conductiveafter the passage of the time period determined by the charging ofcapacitance C4, the voltage at the junction of resistance R5 and R6again goes low since R6 is again shunted by the conductor transistorswitch, thereby de-energizing the controlled load circuit. The charge onmemory capacitance C4 now discharges through the transistor switch03-04, which is again provided with sustaining current throughresistance R8 and diode D2 due to transistor 05 again being renderednon-conductive as a result of the decrease in bias voltage at its base.Because the circuit returns to its normal condition virtuallyinstantaneously, it may be restarted at the end of each cycle withouthesitation.

In the disclosed circuit forming the preferred embodiment of the presentinvention, the values of the various components are as follows:

Resistances Transistors RllOK Ol-ZNSIS) R2 22 meg O2 2N5l32 R3- lKQ32N5l39 R4 330K 04 2N5l32 R55.lK Q52N5l32 R6 3.3K R7 5. I K R8 lOK R9lOK Capacitances Diodes Cl 0.22m Dl 1N9l4 C2 0.0033p.f D2 lN9l4 C30.lp.f C4 0.33;.tf

The controlled load circuit connected to the junction of resistances R5and R6 may consist of a variety of circuits, including variations of thepulse generator 10 which is capable of operating as a flasher inautomotive lighting circuits. The duration of the time period may becontrolled in a number of ways, such as by varying resistance R4 orcapacitance C4, or by varying the frequency of the pulse generator 10,or the width of its output pulses, or by eliminating the frequencydivider circuit. Alternate methods of initiating the timing operationmay be employed. For example, switch SW could be normally closed andconnected in series with diode D2, or in either connection it could bereplaced by a transistor which is controlled by an associated circuit.The circuit embodying the present invention may find numerousapplications. For example, it could be'employed to actuate a warningsignal for a predetermined period of time if a driver leaves hisautomobile with the keys in the ignition.

The advantages of the present invention, as well as certain changes andmodifications of the disclosed embodiment thereof, will be readilyapparent to those skilled in the art. it is the applicant's intention tocover all those changes and modifications which could be made to theembodiment of the invention herein chosen for the purposes of thedisclosure without departing from the spirit and scope of the invention.

What is claimed is:

l A variable-interval timer circuit comprising:

1. pulse-generating means operative to produce, in

synchronization, first and second trains of lowfrequency pulses;

2. timing means comprising:

a. a timing capacitance connected to said pulse generating means toreceive and store said first train of low-frequency pulses; and

b. switching means normally operative to shunt said first train oflow-frequency pulses from said timing capacitance, and to receive saidsecond train of low-frequency pulses to facilitate turn-on of saidswitching means;

3. control means coupled to said timing means and operative normally toprevent said timing capacitance from storing said first train oflow-frequency pulses; and

4. starting means coupled to said control means and operative uponactuation to enable said timing capacitance to store said first train oflow-frequency pulses and, cooperatively with said control means, toproduce an output signal for a predetermined period of time afteractuation of said starting means.

2. A variable-interval timer circuit according to claim 1 wherein saidswitching means is biased by both the voltage on said timing capacitanceand said second train of low-frequency pulses produced by saidpulsegenerating means.

3. A variable-interval timer circuit according to claim 2 wherein saidswitching means is connected to receive said second train oflow-frequency pulses from said pulse-generating means through a couplingcircuit.

4. A variable-interval timer circuit according to claim 3 wherein saidcoupling circuit comprises a resistance and a capacitance connected inseries between said pulse-generating means and said switching means.

5. A variable-interval timer circuit according to claim 1 wherein saidswitching means is maintained normally conductive by sustaining currentprovided by said control means.

6. A variable-interval timer circuit according to claim 5 wherein saidcontrol means comprises:

l. transistor means normally operative to provide said sustainingcurrent to said switching means via a diode, said starting means beingoperative, when actuated, to prevent flow of said sustaining current tosaid switching means; and

2. bias circuit means connected to the input terminal of said transistormeans, and normally partially shunted by said switching means.

7. A variable-interval timer circuit according to claim 6 wherein saidstarting means comprises a normally open switch connected across theoutput terminals of said transistor means.

8. A variable-interval timer circuit according to claim 6 wherein saidbias circuit means comprises a voltage divider formed by a pair ofresistances connected in series, and a resistance connected between thejunction of said voltage divider resistances and the input terminal ofsaid transistor means.

9. A variable-interval timer circuit according to claim 8 wherein onevoltage divider resistance is connected in parallel with said switchingmeans.

1. A variable-interval timer circuit comprising:
 1. pulse-generatingmeans operative to produce, in synchronization, first and second trainsof low-frequency pulses;
 2. timing means comprising: a. a timingcapacitance connected to said pulse generating means to receive andstore said first train of low-frequency pulses; and b. switching meansnormally operative to shunt said first train of low-frequency pulsesfrom said timing capacitance, and to receive said second train oflow-frequency pulses to facilitate turn-on of said switching means; 3.control means coupled to said timing means and operative normally toprevent said timing capacitance from storing said first train oflow-frequency pulses; and
 4. starting means coupled to said controlmeans and operative upon actuation to enable said timing capacitance tostore said first train of low-frequency pulses and, cooperatively withsaid control means, to produce an output signal for a predeterminedperiod of time after actuation of said starting means.
 2. timing meanscomprising: a. a timing capacitance connected to said pulse generatingmeans to receive and store said first train of low-frequency pulses; andb. switching means normally operative to shunt said first train oflow-frequency pulses from said timing capacitance, and to receive saidsecond train of low-frequency pulses to facilitate turn-on of saidswitching means;
 2. A variable-interval timer circuit according to claim1 wherein said switching means is biased by both the voltage on saidtiming capacitance and said second train of low-frequency pulsesproduced by said pulse-generating means.
 2. bias circuit means connectedto the input terminal of said transistor means, and normally partiallyshunted by said switching means.
 3. A variable-interval timer circuitaccording to claim 2 wherein said switching means is connected toreceive said second train of low-frequency pulses from saidpulse-generating means through a coupling circuit.
 3. control meanscoupled to said timing means and operative normally to prevent saidtiming capacitance from storing said first train of low-frequencypulses; and
 4. starting means coupled to said control means andoperative upon actuation to enable said timing capacitance to store saidfirst train of low-frequency pulses and, cooperatively with said controlmeans, to produce an output signal for a predetermined period of timeafter actuation of said starting means.
 4. A variable-interval timercircuit according to claim 3 wherein said coupling circuit comprises aresistance and a capacitance connected in series between saidpulse-generating means and said switching means.
 5. A variable-intervaltimer circuit according to claim 1 wherein said switching means ismaintained normally conductive by sustaining current provided by saidcontrol means.
 6. A variable-interval timer circuit according to claim 5wherein said control means comprises:
 7. A variable-interval timercircuit according to claim 6 wherein said starting means comprises anormally open switch connected across the output terminals of saidtransistor means.
 8. A variable-interval timer circuit according toclaim 6 wherein said bias circuit means comprises a voltage dividerformed by a pair of resistances connected in series, and a resistanceconnected between the junction of said voltage divider resistances andthe input terminal of said transistor means.
 9. A variable-intervaltimer circuit according to claim 8 wherein one voltage dividerresistance is connected in parallel with said switching means.